ptwm_core::codecs::order1_arithmetic
ptwm_core::codecs::order1_arithmetic
Order1Arithmetic: static order-1 (lag-1) arithmetic coder over the exponent byte plane — a learned dynamic-length float coder. Fits a conditional table once, serializes it into codec state (the static table is what makes a future GPU decode kernel feasible), and range-codes against the frozen model. Self-delimiting: it frames the true plane length and ignores the container's source-derived decoded_len.
ptwm_core::codecs::order1_arithmetic
crates/ptwm-core/src/codecs/order1_arithmetic.rs:1mod order1_arithmeticOrder1Arithmetic: static order-1 (lag-1) arithmetic coder over the exponent byte plane — a learned dynamic-length float coder. Fits a conditional table once, serializes it into codec state (the static table is what makes a future GPU decode kernel feasible), and range-codes against the frozen model. Self-delimiting: it frames the true plane length and ignores the container's source-derived `decoded_len`.
ptwm_core::codecs::order1_arithmetic::Order1Arithmetic
crates/ptwm-core/src/codecs/order1_arithmetic.rs:21pub struct Order1Arithmetic;neural_predictor
Opt-in NNCP-style neural-predictor plane codec. Stateless; self-delimiting (the coder frames the plane length, so decode ignores decoded_len). NOT in the default dispatch menu — selected only when named in codec_menu.
order1_scale_ac
Order1ScaleAC: per-row lag-1 conditional arithmetic coder over the SCALE plane of MXFP4 / NVFP4 tensors.